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W19B320AT/B
6.3 Write Operation Status
The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3,
DQ5, DQ6, and DQ7. Each of DQ7 and DQ6 provides a method for determining whether a program or
erase operation is complete or in progress. The device also offers a hardware-based output signal,
RY/#BY, to determine whether an Embedded Program or Erase operation is in progress or has been
completed.
6.3.1
DQ7: #Data Polling
The #Data Polling bit, DQ7, indicates whether an Embedded Program or Erase algorithm is in
progress or completed, or whether or not a bank is in Erase Suspend. Data Polling is valid after the
rising edge of the final #WE pulse in the command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 and the complement of the data
programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. Once the
Embedded Program algorithm has completed that the device outputs the data programmed to DQ7.
The system must provide the program address to read valid status information on DQ7. If a program
address falls within a protected sector, #Data Polling on DQ7 is active for about 1 μ s, and then that
bank returns to the read mode.
During the Embedded Erase algorithm, #Data Polling produces “0” on DQ7. Once the Embedded
Erase algorithm has completed, or when the bank enters the Erase Suspend mode, #Data Polling
produces “1” on DQ7. An address within any of the sectors selected for erasure must be provided to
read valid status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected, #Data
Polling on DQ7 is active for about 100 μ s, and then the bank returns to the read mode. If not all
selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and
ignores the selected sectors that are protected. However, if the system reads DQ7 at an address
within a protected sector, the status may not be valid.
Just before the completion of an Embedded Program or Erase operation, DQ7 may change
asynchronously with DQ0-DQ6 while Output Enable (#OE) is set to low. That is, the device may
change from providing status information to valid data on DQ7. Depending on when it samples the
DQ7 output, the system may read the status or valid data. Even if the device has completed the
program or erase operation and DQ7 has valid data, the data outputs on DQ0-DQ6 may be still
invalid. Valid data on DQ0-DQ7 will appear on successive read cycles.
6.3.2
RY/#BY: Ready/#Busy
The RY/#BY is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in
progress or complete. The RY/#BY status is valid after the rising edge of the final #WE pulse in the
command sequence. Since RY/#BY is an open-drain output, several RY/#BY pins can be tied together in
parallel with a pull-up resistor to V DD .
When the output is low (Busy), the device is actively erasing or programming. (This includes programming
in the Erase Suspend mode.) When the output is high (Ready), the device is in the read mode, the standby
mode, or one of the banks is in the erase-suspend-read mode.
6.3.3
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or
complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any
address, and is valid after the rising edge of the final #WE pulse in the command sequence (before the
program or erase operation), and during the sector erase time-out.
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功能描述:IC FLASH 32MBIT 70NS 48TSOP RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 产品变化通告:Product Discontinuation 26/Apr/2010 标准包装:136 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步，DDR II 存储容量:18M（1M x 18） 速度:200MHz 接口:并联 电源电压:1.7 V ~ 1.9 V 工作温度:0°C ~ 70°C 封装/外壳:165-TBGA 供应商设备封装:165-CABGA（13x15） 包装:托盘 其它名称:71P71804S200BQ